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Principal Engineer - FPGA/ASIC Design at Jobgether. This position is posted by Jobgether on behalf of a partner company. We are currently looking for a Principal Engineer - FPGA/ASIC Design in the United States.. We are seeking a Principal Engineer specializing in FPGA and ASIC design to drive the development of advanced digital systems in mission-critical applications. This role involves architecting, coding, simulating, and verifying complex FPGA/ASIC solutions for high-reliability electronic control systems. The ideal candidate will work closely with cross-functional engineering teams to implement innovative solutions, ensure compliance with industry standards, and support both testing and deployment across multiple sites. This position offers the opportunity to solve challenging technical problems while contributing to the design of next-generation hardware systems in a collaborative, hybrid work environment.. Accountabilities. . Lead the design, development, verification, integration, and testing of FPGA and ASIC solutions for electronic control systems.. . Develop RTL using VHDL, Verilog, or SystemVerilog, and perform simulations to validate designs.. . Create detailed design documentation, verification plans, and test benches in compliance with relevant industry standards.. . Achieve timing closure, optimize power utilization, and ensure performance and reliability of FPGA/ASIC designs.. . Evaluate design flows, including synthesis, place and route, and timing constraints.. . Collaborate with engineering teams across multiple sites, supporting lab testing and debugging activities.. . Apply scripting and automation using languages such as TCL, Python, or Shell scripts to improve workflows.. . Participate in system-level modeling and design using tools like MATLAB, Simulink, or SysML.. . Maintain accurate records and documentation to support certification and project review processes.. . . Bachelor’s degree in Electronics Engineering, Computer Engineering, or related field with 5+ years of experience, or Master’s with 3+ years, or PhD in a relevant discipline.. . U.S. citizenship is required for this role.. . Proven experience in FPGA/ASIC design, verification, and lab validation using tools such as Xilinx or Actel flows.. . Strong proficiency in hardware description languages (VHDL, Verilog, SystemVerilog) and RTL design methodologies.. . Familiarity with FPGA timing closure, test bench development, and simulation tools.. . Experience in Windows and Linux development environments, version control (Git, SVN), and scripting languages.. . Knowledge of model-based design, systems engineering, and SysML modeling tools such as Cameo Systems Modeler (MagicDraw).. . Strong problem-solving, communication, and documentation skills to convey complex technical information to multiple stakeholders.. . Company Location: United States.