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Staff Engineer - (Remote - India) at Jobgether. This position is posted by Jobgether on behalf of Alphawave IP inc. We are currently looking for a Staff Engineer - STA in India.. In this role, you will play a key part in driving timing convergence for complex SoCs, ensuring high performance and reliable tape-outs across advanced technology nodes. You will collaborate with cross-functional teams, contribute to methodology development, and manage timing closure for multi-mode and multi-corner designs. This position offers the opportunity to lead impactful engineering projects while working in a flexible, collaborative environment that values innovation, precision, and professional growth.. . Accountabilities. As a Staff Engineer - STA, you will:. . Lead static timing analysis (STA) setup, reviews, and sign-off for multi-mode, multi-corner, and multi-voltage domain designs.. . Develop and maintain constraints for block and SoC hierarchical designs across multiple modes.. . Drive timing closure at the full-chip level, supporting physical design teams on block and subsystem convergence.. . Collaborate with design, DFT, IP, and PD teams to resolve constraint conflicts and ensure robust timing strategies.. . Guide clock tree synthesis (CTS) methodologies and provide strategic input to implementation teams.. . Manage ECO generation and implementation methodologies to achieve timing closure.. . Support gate-level simulations and verification enablement.. . Create automation scripts to enhance STA methodologies and processes.. . To be successful in this role, you should bring:. . 7–14 years of experience in synthesis and STA for full-chip sign-off and tape-outs.. . Hands-on expertise with both block-level and full-chip timing constraints for hierarchical designs.. . Strong knowledge of DFT constraints and ASIC physical design implications on timing.. . Experience with Synopsys/Cadence tools, advanced node technologies, and variation/aging-aware design sign-off.. . Solid understanding of timing budgets, CTS methodologies, and power/timing/area trade-offs.. . Proficiency in scripting languages such as Perl, TCL, or Python.. . Familiarity with multi-voltage designs using CPF/UPF and power analysis with PTPX.. . Knowledge of VHDL/Verilog constructs, RTL debugging, and IP-level verification.. . Excellent communication skills, with the ability to explain complex technical issues clearly.. . A collaborative mindset with enthusiasm for problem-solving and teamwork.. . Company Location: India.