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FPGA Digital Design Engineer at Kepler Communications. Location Information: . Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new era of data-driven intelligence and innovation. With. 33 satellites launched to date,. Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. . We’re on the hunt for a top-tier . FPGA Digital Design Engineer. to develop the next generation of our satellites.. . At Kepler, you’ll have the opportunity to work with a dedicated team of engineers building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA code either with a focus on DSP algorithms to modulate and demodulate signals on board our software defined radio (SDR), or embedded systems interfacing with processors and peripherals. To be effective you will need to participate in all phases of FPGA design flow (Simulation, Synthesis, Place & Route, Timing Closure and Hardware Testing). A good understanding of the intricacies of FPGA development would make a candidate standout.. . Key Responsibilities:. . Develop custom IP for new features of the Kepler satellite digital payloads. . Iterate on current DSP and interface designs to improve reliability. . Work with IP core vendors to integrate new functionality into the Kepler designs. . Work with lead engineers in developing the communications and network architecture of our future satellite constellation. . Participate in conceptual design studies of new spacecraft. . Required Skills & Qualifications:. . Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent. . 5+ yr. working experience with FPGA/RTL design. . Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog. . Xilinx FPGA(s). Specifically, Zynq and UltraScale. . Solid understanding of timing principles, including clock domain crossing and timing closure. . Strong scripting skills (e.g Python, Tcl, csh/bash, etc.). . Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim). . Bonus Points:. . Masters of Science in Computer/Electrical Engineering, or equivalent. . Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM. . Experience with memory mapped interfaces such as AXI, Wishbone, Avalon. . Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA. . Experience with Linting tools, . Questa Sim. or Riviera-Pro. . Experience with . Xilinx Versal and RFSoC.  . . Experience designing printed circuit boards. . Knowledge of radio-frequency electronics design. . Salary Range: $131,00 - $181,000 CAD. . Actual total compensation will be determined at the Company’s discretion and is based on a variety of job-related factors, which may include, but are not limited to, relevant knowledge, skills, experience, performance, and education and/or training. The Company encourages all qualified applicants to apply, even if the posted salary range does not align with their expectations, as it does not reflect our total compensation package.. . Job Type: This is for a current vacancy. . Kepler Communications is committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. We welcome applications from: Women, Aboriginal persons, persons with disabilities, ethnic minorities, visible minorities, people who identify as LGBTQ+ and others who may contribute to diversification in our workplace.. . As part of our commitment to accessibility for all persons with disabilities, Kepler will, upon the request of the applicant, provide accommodation during the recruitment process to ensure equal access to applicants with disabilities. Please contact our People & Culture team, through our . Career Page. to make your accommodation needs known and we will consult with you to ensure suitable accommodation is provided.